1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, filled with an appropriate metal. The vias provide electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of a plurality of stacked layers. As the complexity of integrated circuits advances and brings about the necessity for conductive lines that can withstand moderately high current densities, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum with a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper and alloys thereof are materials that are increasingly used to replace aluminum due to their superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. Despite these advantages, copper and copper alloys also exhibit a number of disadvantages regarding the processing and handling in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called inlaid or damascene technique (single and dual) is preferably used, wherein a dielectric layer is first applied and then patterned to receive trenches and/or vias, which are subsequently filled with copper or copper alloys.
It turns out that the process of forming vias and trenches in the dielectric material of the respective metallization layer according to the damascene regime may significantly affect the overall production yield during the formation of advanced semiconductor devices having copper-based metallization layers owing to delamination issues and etch-related geometry effects.
With reference to FIGS. 1a-1d, a typical conventional process flow will now be described in more detail so as to more clearly demonstrate the problems involved in forming highly scaled metal lines in a dielectric material according to a damascene process, for instance, a dual damascene process, in which vias are formed prior to corresponding trenches connected to the vias, wherein this approach is often called a “via first/trench last” approach.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 comprising a substrate 101, which may be provided in the form of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate and the like, wherein the substrate 101 may also represent a device layer having formed therein individual circuit elements, such as transistors, capacitors, lines, resistors, contact portions and the like. For convenience, any such circuit elements are not shown in FIG. 1a. The device 100 comprises a first device region 120A and a second device region 120B, wherein the first device region 120A may represent an “inner” region that receives metal lines and vias, whereas the second device region 120B may represent a device region for receiving a large metal area in the respective metallization layer together with corresponding metal lines in the first device region 120A. For example, a measurement region and the like may be formed in the second device region 120B, as is typically provided for evaluating so-called dishing effects occurring during the removal of excess copper by chemical mechanical polishing (CMP).
The device 100 further comprises a dielectric layer 102 formed above the substrate 101, wherein the layer 102 may represent a dielectric material enclosing the individual circuit elements, also referred to as a contact material, or the layer 102 may represent a portion of a lower-lying metallization layer, in which any metal-filled lines may be embedded. Depending on the specific design of the device 100, or the function of the layer 102, it may be comprised of a conventional dielectric material such as silicon dioxide, silicon nitride, or it may comprise a low-k dielectric material such as, for instance, hydrogen-enriched silicon oxycarbide (SiCOH) and the like. A metal line 103A is formed within the first device region 120A and above the substrate 101 and at least partially within the layer 102 for establishing an electric connection to circuit elements formed within the first device region 120A. The metal line 103A may be comprised of a copper-containing metal including conductive barrier layers (not shown) so as to enhance adhesion of the metal line 103A to the surrounding material and reduce diffusion of copper into sensitive device regions. An etch stop layer 104 is formed on the dielectric layer 102 and the metal line 103A, wherein the etch stop layer 104 may be comprised of a material that exhibits a high etch selectivity to the material of a dielectric layer 105 formed on the etch stop layer 104. Furthermore, the etch stop layer 104 may also act as a diffusion barrier between the metal line 103A and neighboring materials to reduce the out-diffusion of metal, such as copper, and diffusion of dielectric material into the metal line 103A.
The dielectric layer 105, which may be comprised of a low-k dielectric material, is formed on the etch stop layer 104, followed by an anti-reflective coating (ARC) layer or capping layer 106, which may be formed from two or more sub-layers so as to achieve the desired performance with respect to the optical behavior, mechanical strength and masking characteristics. For instance, the capping layer 106 may be provided as a stack including a silicon dioxide layer (acting to impart improved mechanical strength to the layer 105 when formed of a low-k material), a silicon oxynitride layer for adapting the optical behavior and a thin silicon dioxide layer acting as a nitrogen barrier for a resist mask 107 formed on the capping layer 106. The resist mask 107 includes a first opening 107A above the first device region 120A that corresponds to a via opening 105A for electrically connecting the metal line 103A with a metal line still to be formed in the dielectric layer 105.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After the fabrication of any circuit elements within the substrate 101, the dielectric layer 102 may be deposited by well-established deposition recipes based on plasma enhanced chemical vapor deposition (PECVD). For example, the layer 102 may be comprised of silicon dioxide, fluorine-doped silicon dioxide or SiCOH and hence deposition recipes on the basis of appropriate precursors may be employed to form the layer 102. Then, the metal line 103A may be formed in accordance with processes as will be described in the following with reference to the layer 105. Thereafter, the etch stop layer 104 is deposited by, for instance, well-established PECVD techniques with a thickness that is sufficient to reliably stop a via and trench etch process to be performed later on. Next, the dielectric layer 105 is formed by CVD or spin-coating, depending on the material used. Then, the capping layer 106 is formed by PECVD techniques on the basis of well-established recipes to provide the desired characteristics in the further processing of the device 100. Finally, the resist mask 107 may be formed by advanced photolithography to form the respective opening 107A. Thereafter, an anisotropic etch process is performed, wherein, in an initial phase, the exposed portion of the layer 106 is removed and, in a subsequent process, the dielectric material of the layer 105 is removed to form the via opening 105A.
FIG. 1b schematically illustrates the device 100 in an advanced manufacturing stage. The device 100 now comprises a resist mask 109 having formed therein a trench 109A above the via opening 105A with dimensions corresponding to design dimensions of a metal line to be formed above and around the via opening 105A. The resist mask 109 further comprises an opening 109B in the second device region 120B formed in accordance with the design dimensions for a corresponding metal region, such as a test region, wherein the dimensions of the opening 109B may be significantly greater compared to the dimension of the trench 109A, at least in one dimension. For instance, the opening 109B may have a design dimension of 100 μm×100 μm in advanced semiconductor devices of minimal critical dimensions of 50 nm or even less. Moreover, a fill material 108 is formed underneath the resist mask 109, wherein the fill material 108 is also provided within the opening 105A. The fill material may be comprised of a photoresist of different type compared to the resist mask 109, or the fill material 108 may represent any other polymer material that may be applied in a low viscous state to fill the opening 105A while providing a substantially planar surface. The fill material 108 may also serve as an ARC layer during the patterning of the resist mask 109.
The resist mask 109 may be formed by first applying the fill material 108 by, for example, spin-coating a resist or a polymer material, then applying a photoresist by spin-coating, performing a well-established photolithography process and etching or dry-developing the fill material 108 on the basis of the resist mask 109. Thereafter, the device 100 is subjected to an etch ambient 110 on the basis of carbon and fluorine to etch through the layer 106 and remove a portion of the layer 105 to form a trench around the via opening 105A and an opening in the second device region 120B corresponding to the opening 109B, while the fill material 108 in the via opening 105A prevents substantial material removal therein. Moreover, the fill material 108 within the opening 105A, although partially removed during the etch process 110, protects the remaining etch stop layer 104 in the opening 105A so that the metal line 103A is not exposed to the etch ambient 110. Thereafter, a trench of specified depth is formed around the via opening 105A and a corresponding opening in the second device region 120B, the resist mask 109 and the fill material 108 are removed by, for instance, an oxygen-based plasma treatment.
During the etch process 110, the removal rate for material of the dielectric layer 105 may significantly depend on the geometric structure of the trenches and openings to be formed in the dielectric layer 105. For example, the etch rate at the trench opening 109A, when for instance representing an isolated trench, may be significantly higher compared to the rate at the opening 109B designed to represent a test region. Generally, in modern semiconductor devices, substantially continuous non-tiled metal plates of increased dimensions compared to metal lines in product areas may be required for a variety of test and measurement tasks. Consequently, due to the structure and geometry dependent etch behavior, the etch depth and thus the finally achieved thickness of the large-area metal regions may be reduced compared to actual metal lines, thereby potentially resulting in an overall reduced stability of the respective metallization layer.
FIG. 1c schematically shows the device after the above process sequence with a trench 111A and an opening 111B formed in the layer 106 and the dielectric layer 105 in the first and second device regions 120A and 120B, respectively. Moreover the device is subjected to a further etch process 112 to remove the remaining etch stop layer 104 to thereby connect the via opening 105A to the metal region 103. The via opening 105A, the trench 111A and the opening 111B may then be filled with metal, such as copper or copper alloys, by electrochemical deposition techniques, wherein, prior to the electrochemical deposition, corresponding barrier and seed layers may be formed.
FIG. 1d schematically depicts the device 100 after completion of the above-described process sequence. Thus, the device 100 comprises a metal-filled via 113A connecting to the metal region 103 and a metal line 112A formed above the via 113A. In the second device region 120B, a metal area 112B is formed, whose thickness may be reduced compared to the thickness of the metal line 112A due to potential etch non-uniformities during the etch process 110, as previously explained. Moreover, the metal area 112B may exhibit a reduced adhesion to the adjacent dielectric material of the layer 105, which may cause delamination of metal during manufacturing processes after the metal deposition, such as CMP and the like, during which increased mechanical stress may be applied to the device 100. Consequently, production yield may be compromised and device performance reduced.
In view of the situation described above, there exists a need for an improved technique which solves or at least reduces the effects of one or more of the problems identified above.